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MT90210
Multi-Rate Parallel Access Circuit Preliminary Information
Features
* Parallel-to-serial and serial-to-parallel conversion of up to 1536 full duplex channels or 3072 time-slots Serial port data rates selectable between 2.048, 4.096 or 8.192 Mb/s Provides a mechanism for a double buffer function to be implemented in external memory 24 serial I/O lines programmable in different modes: 12 in/12 out at 8.192 Mb/s (1536 full duplex channels) or 24 bidirectional line modes for 2.048 and 4.096 Mb/s Provides a bidirectional 8-bit parallel port operating at 16.384 or 32.768 MByte/s for direct interface to external memory (dual port) Provides an external 13-bit output address bus for direct connection with an 8K-position dual port memory JTAG boundary scan
DS5026 ISSUE 2 August 1998
Ordering Information MT90210AL 100 Pin PQFP
* * *
-40 to +85C
Description
The MT90210 is a 100-pin device used to interface a parallel bidirectional 8 bit bus to 24 time division multiplexed (TDM) serial streams. The device is configured to perform simultaneous parallel-to-serial and serial-to-parallel conversion with the capability of handling up to 3072 channels, 1536 on the transmit and 1536 on the receive direction. Depending on the operation mode selected at the mode pins, the individual 64 Kb/s channels on the serial links may be configured as inputs or outputs. The data on the parallel bus is in a format suitable for interfacing with a dual-port RAM. Depending on the data rate selected by the MD0-MD2 input pins, serial data is clocked in and out on the serial streams at either 2.048, 4.096 or 8.192 Mb/s.
*
*
*
Applications
* * * * Fast access to ST-BUS, SCSA, MVIP, and H-MVIP serial backplanes Voice processing cards for Computer Telephony Integration (CTI) Video and teleconferencing bridge cards Fast DSP access to serial TDM buses
RDin Strobe RBC R/W1 R/W2
S0
External Memory Access Control Shift Registers Timing Generation Address Generator Write Counter Counter
Read
P0 * * P7 WBC SCLK HC4 C16C16+ F0i PCLK PLLVSS LP1,LP2 PLLAGND CKout RST PLLVDD
* * * * * * * *
S23
Analog PLL
Boundary Scan Test
MUX Mode Control
TDI TCK TMS TRST TDO
Figure 1 - Functional Block Diagram
2-145
A12
A0
OEser MD2 MD1 MD0
* * * * * * * *
MT90210
Preliminary Information
A6 A7 VSS A8 A9 VDD A10 VSS A11 A12 RBC VDD VSS WBC S0 S1 S2 VSS VDD S3
80 82
A5 VSS VDD A4 A3 A2 VSS A1 A0 VDD Strobe VSS P7 P6 P5 VSS P4 VDD P3 P2 VSS P1 P0 R/W2 R/W1 VDD2 CKout PCLK RST PLLVDD
78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 84 46 86 44 88 42 90 92 94 36 96 34 98 32 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 40 38
100 PIN PQFP
PLLAGND LP1 LP2 PLLVSS IDDTN TD VSS2 C16C16+ VDD2 MD0 MD1 MD2 F0i TRST TCK TMS TDI HC4 SCLK
Note: the PQFP package meets the JEDEC standard MO-108, CC1. Critical dimensions: Lead pitch = 0.65mm, Body Size = 14mm x 20mm, Package size = 17.9mm x 23.9mm.
Pin Description
Pin 95-97, 100, 1-3, 6 7-9, 11-15 18-22, 24-26 27 29 30 Name S0-S2, S3, S4-S6, S7 S8-S10, S11-S15 S16-S20 S21-S23 TDO RDin OEser Description Serial Lines 0-7 (TTL compatible with internal pullups in the range 25 - 125k). Bidirectional, time division multiplexed serial streams. According to mode selected by MD0-2 inputs, distinct data rates can be selected at the serial port. In mode 3, these lines are configured as inputs only. In modes 1, 2, 4 and 5, these lines become bidirectional. Serial Lines 8-15. See description for S0-S7 above. In mode 3, S8-S11 are inputs and S12-S15 are outputs. In modes 1, 2, 4 and 5 these are bidirectional lines. Serial Lines 16-23. See descripton for S0 - S7 above. For mode 3, these lines are outputs and operate at 8.192 Mb/s rates. When operating in modes 1, 2, 4 and 5, these lines are bidirectional. Boundary Scan Test Data Output. Read P0-P7 input clock. This input is used by the MT90210 to sample bytes coming in at the parallel port P0-P7 lines. Typically, the user should connect CKout to this input. Serial Port Output Enable (Input). On the parallel-to serial conversion direction, this input is used by the MT90210 to know which time-slots on the serial output streams will be placed in high-impedance. This input is sampled synchronously along with the parallel input data before the parallel-to-serial conversion takes place. When low, output serial channels are actively driven. When set high, the output bus drivers are disabled.
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S4 S5 S6 VDD VSS S7 S8 S9 S10 VSS S11 S12 S13 S14 S15 VDD VSS S16 S17 S18 S19 S20 VSS S21 S22 S23 TDO VSS2 RDin OEser
Figure 2 - Pin Connections
Preliminary Information
Pin Description (continued)
Pin 31 Name SCLK Description
MT90210
Serial Port Clock (input). The SCLK clock is used to control the serial port operation in modes 1,2,3 and 4. Depending on the operation mode selected at the MD0-MD2 inputs, this input can accept 4.096 (MD2-0=000), 8.192 (MD2-0=001) or 16.384 (MD2-0 =010 and 011) MHz clock. In mode 5, this input is ignored. H-MVIP C4. This is a 4.096 MHz clock utilized in modes 4 and 5 to maintain compatibility with existing MVIP-90 systems. It is utilized to sample the frame pulse input (F0i). Not used in Modes 1 - 3. Boundary Scan Test Data Input. Boundary Scan Test Mode Select. Boundary Scan Test Clock. Boundary Scan Test Reset. Frame Synchronization Signal (TTL compatible input). This input signal establishes the frame boundary for the serial input/output streams.
32
HC4
33 34 35 36 37 38-40
TDI TMS TCK TRST F0i
MD2-MD0 Operation Mode Bits 0-2 (Input). Selects the data rate for the time division, multiplexed serial streams. 2.048 (mode 1, MD2-0=000), 4.096 (mode 2, MD2-0=001) or 8.192 (mode 3, MD2-0=010) Mb/s data rates are available. When MD2-0 are set to 011 (mode 4), the MT90210 operates in mixed data rates mode where S16-23 operate at 8.192 Mb/s and the remaining serial streams run at 2.048 Mb/s. In mode 5 (MD2-0=100), the MT90210 operates as per mode 4 but the device will accept a differential clock reference at 16.384 MHz at pins C16+ and C16-. C16+ C16TD IDDTN PLLVSS LP2 LP1 Serial Port Clock Input. In mode 5 (MD2-0= 100), this is a 16.384 MHz differential signal. Note used in Modes 1 - 3. Serial Port Clock Input. The complement to C16+. Reserved - Do not connect. Connect to Ground. PLL Ground Input. Loop Filter Input. An external RC circuit is required at this input, refer to Figure 10. Loop Filter Input. An external RC circuit is required at this input, refer to Figure 10.
42 43 45 46 47 48 49 50 51 52 53 54
PLLAGND PLL Analog Ground output. Provides ground to PLL loop filter, refer to Figure 10. PLLVDD RST PCLK CKout PLL Power Input. +5V RESET. A low on this pin resets the device. Parallel Port Clock Input. CKout must be connected to this input. Internal VCO Output Signal. Output of internal PLL frequency multiplier. In mode 1 the frequency is 16.384 MHz, for the other modes the frequency is 32.768 MHz. Must be connected to PCLK only. Read/Write Output 1. This output signal toggles low for the last half of a memory write cycle indicating valid data. Read/Write Output 2. This output is low for memory read operations and high for memory write operations.
56 57
R/W1 R/W2
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MT90210
Pin Description (continued)
Pin 58-59, 61-62, 64, 66-68 70 Name P0-P1, P2-P3, P4, P5-P7 Strobe Description
Preliminary Information
Parallel Input/Output Data Bus. This 8 bit data bus is a bidirectional parallel port used to perform 8-bit transactions between the MT90210 and the external dual port RAM. Data is clocked in and out of the P0-P7 parallel port according to Figures 22 and 23. Strobe Output. This output is typically connected to the Chip-enable input of the external dual port RAM. It is kept low during all read cycles, stays high during inactive periods and goes low for the last half of a memory write cycle. External Memory Address Outputs A0-A12. These 13 address output lines are provided by the MT90210 to allow a direct connection to an external dual port RAM.
72-73, 75- 77, 80-82, 84-85, 87, 89-90 91
A0-A1, A2-A4, A5-A7, A8-A9, A10, A11-A12 RBC
Read Data Block Complete (output). A transition on this output is used to notify the external CPU that the MT90210 has finished reading the contents of one entire 125s frame from the external dual port memory (e.g.; from addresses 0000h to 0FFFh in modes 3, 4 or 5). Whenever RBC toggles, the MT90210 starts reading the next half of the memory (addresses 1000h to 1FFFh) while the local CPU updates the first half with more data to be sent. RBC toggles every 125s. When this signal is low, the MT90210 is reading the lower memory block. Write Data Block Complete (Output). A transition on this output is used to notify the external CPU that the MT90210 has finished writing the contents of one entire 125s frame into the external dual port memory (e.g; from addresses 0000h to 0FFFh in modes 3,4 or 5). Once WBC toggles, the local CPU can access the Dual port memory to get the data while the MT90210 writes the contents of the next 125s frame into the other half (addresses 1000h to 1FFFh) of the dual port memory. WBC toggles every 125s. When this signal is low, the MT90210 is writing to the lower memory block. Supply Input. +5V.
94
WBC
4,16, 63, 71, 78, 86, 92, 99 41, 55 5,10, 17, 23, 60, 65, 69, 74, 79,83, 88, 93, 98 28
VDD
VDD2 VSS
Supply Input. +5V. Ground.
VSS2
Ground.
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Preliminary Information
Functional Description
The MT90210 is a 100-pin device that converts incoming serial telecom streams of 2.048, 4.096 or 8.192 Mb/s on to an 8-bit parallel bus, and converts input data on this parallel bus to the outgoing serial telecom links. The device is configured to perform simultaneous parallel-to-serial and serial-to-parallel conversion. MT90210 interfaces up to 24 bidirectional serial data streams to a byte oriented parallel port for access by a dual-port RAM. It contains an address generator for parallel port read and write operations directly to an external dual port memory. A single MT90210 device can handle up to 3072 channels, 1536 on the transmit and 1536 on the receive direction. Depending on the operation mode selected at the mode pins (MD0-MD2), the 64 kb/s serial telecom channels may be configured as inputs or outputs. The data on the parallel bus is in a format suitable for interfacing with popular dual port memories. Depending on the data rate selected by the MD0MD2 input pins, serial data is clocked in and out on the serial streams at either 2.048, 4.096 or 8.192 Mb/s, as shown in Figure 6. A mechanism for implementing external double buffering is provided by the Write Block Complete (WBC) and Read Block Complete (RBC) output pins. Double buffering the data allows the processor to independently access an entire frame of data in the external memory while the MT90210 reads or writes the complementary frame in the memory. For example, in mode 3 (Figure 4), during the first frame the MT90210 will read and write in to the first half of the memory space (Block 0) and during the second frame the MT90210 will read and write in to the second half of the memory space (Block 1). Within each block the transmit data and receive data are separated and located at fixed address locations. The operation of WBC and RBC is shown in Figures 7a and 7b. On the external memory port side, the device performs 8-bit wide operations with a cycle time of 30 or 61 ns. The parallel port operates at 16.384 MByte/s (for mode 1) or 32.768 MByte/s (for modes 2,3,4 and 5). To create the high speed clock required to manage the byte operations at the parallel port, a built in PLL multiplies the serial port input clock (SCLK) by a factor of two or four depending on the mode. In all operation modes, the user should connect the PLL CKout to PCLK input. A separate input pin, Output Enable serial (OEser pin 30), may be used to selectively tristate individual 64Kb/s serial links. By using a 9-bit external dual
MT90210
port RAM and connecting the ninth bit to OEser as shown in Figure 9, the processor may disable an individual channel by setting the ninth bit for that channel in the transmit (TX) portion of the current block. The remaining 8 bits for this channel may be any value since they are ignored by the MT90210 when the ninth bit is 1. To avoid contention on the serial bus, it is recommend that the user configure all serial streams as inputs at start-up. This may be done by setting all OEser bits to 1 in the TX portions of both memory blocks. In mode 3, the serial streams are permanently configured as 12 inputs and 12 outputs, and the state of OEser is ignored. An Overview of CTI bus protocols Multi-Vendor Integration Protocol (MVIP) provides a coherent approach to building solutions for worldwide markets by merging computing and communications technologies under one open architecture. MVIP ensures inter-operability among telephone-based resources (such as trunk interfaces, voice, video, fax, text-to-speech, speech recognition) for use within a computer chassis in an individual or networked configuration. H-MVIP addresses the need for higher telephony traffic capacity in individual computer chassis. H-MVIP defines three major items that together make a useful digital telephony transport and switching environment: the H-MVIP digital telephony bus with up to 3072 "time-slots" of 64 Kb/s each; a bus interface with digital switching that allows a group of H-MVIP interfaced circuit boards to provide complete, flexible, distributed telephony switching; and a logical device driver model and standard software interface to a logical model. Operating Modes The MT90210 device can operate in one of five modes appropriate for different application needs. Mode selection must be done while the device is in reset (RST low and a valid clock applied to the PCLK input). These modes are explained in the following paragraphs. Mode 1: The serial input/output format conforms to the ST-BUS requirements when the data rate is 2.048 Mb/s (see Figure 6). Serial port clock (SCLK) is 4.096 MHz. The on-chip PLL produces a phase locked 16.384 MHz clock (CKout) from the SCLK input. In this data rate operation, the 24 serial lines (S0-23) become bidirectional links at 2.048 Mb/s. The ST-BUS is a time-division multiplexed serial bus with 32, 8-bit channels per frame. Frame boundaries are delineated by the frame pulse. Figure 3 depicts
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MT90210
how the data from the serial port is mapped into the external dual port memory.
Preliminary Information
1536 bytes for TX 768 bytes for TX
0000 05FF 0800 0DFF 1000 15FF 1800 1DFF 1FFF
0000 02FF 0400 06FF 0800 0AFF 0C00 0EFF 0FFF
BLOCK 0
1536 bytes for RX 1536 bytes for TX
BLOCK 0
768 bytes for RX 768 bytes for TX
BLOCK 1
1536 bytes for RX
BLOCK 1
768 bytes for RX
MODES 2 & 3 24 bidirectional streams at 4.096Mb/s, or 12 in / 12 out at 8.192Mb/s Address outputs used: A0-A12 Legend: unused memory space
MODE 1 24 bidirectional streams at 2.048Mb/s Address outputs used: A0-A11; A12 always zero. Legend: unused memory space
Figure 4 - Dual Port RAM Memory Map for Modes 2 and 3 Mode 4: The MT90210 is configured such that the 24 serial streams are bidirectional and split into two different functional groups: (i) streams S0-S15 operate at 2 Mb/s rate (512 timeslots), (ii) S16-S23 operate at 8.192 Mb/s rate (1024 timeslots). Memory mapping for mode 4 is described in Figure 5. For compatibility with legacy MVIP timing, mode 4 provides an additional clock input at 4.096 MHz (HC4 input pin) which allows the device to detect frame sync pulse (F0i) with a typical width of 244 ns. In mode 4, the 16.384 (SCLK) and 4.096 (HC4) MHz clocks should be in sync according to H-MVIP specifications. The on-chip PLL doubles SCLK to produce a CKout signal of 32.768 MHz. Figure 13 and Table 4 show the write and read operations on the parallel port at the frame boundary. Mode 5: Identical operation as per mode 4 with the difference that the 16.384 MHz clock is a differential signal received at the two input pins, C16+ and C16of the MT90210 device. The differential clock is needed to eliminate distortion in the clock signal passing through a ribbon cable as per H-MVIP specification. The SCLK input is not used in this mode. Memory mapping for mode 5 is depicted in Figure 5.
Figure 3 - Dual Port RAM Memory Map for Mode 1 Mode 2: When the device is configured for 4.096 Mb/s data rate operation, each of the 24 timedivision multiplexed serial streams is made up of 64 channels. In this data rate operation, the 24 serial lines (S0-23) become bidirectional links at 4.096 Mb/s. Serial port clock (SCLK) is 8.192 MHz. The on-chip PLL produces a phase locked 32.768 MHz clock (CKout) from the SCLK input. Figure 4 depicts how the data from the serial port is mapped into the external dual port memory. Mode 3: When the device is configured for 8.192 Mb/s data rate operation, each of the 24 timedivision multiplexed serial streams is made up of 128 channels. In this mode, bidirectional operation on the serial port streams is not provided and the MT90210 is set in a 12 in / 12 out configuration and the OEser input is ignored. Streams S0-S11 are configured as inputs, and S12-S23 are configured as outputs. Serial port clock is 16.384 MHz. The on-chip PLL doubles this clock to produce a CKout clock of 32.768 MHz. Figure 4 depicts how the data from the serial port is mapped into the external dual port memory. Figure 12 and Table 3 show the write and read operations on the parallel port at the frame boundary.
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Preliminary Information
MT90210
0000 01FF 0400
512 bytes for S0-S15 TX
Functional operation of the MT90210 device at the parallel interface for modes 1, 2, and 3
Figures 8, 12, and 13 depict the parallel port READ and WRITE operation of the MT90210 device. The state of the signals R/W1, R/W2 and Strobe defines a valid Read or a valid Write operation. During a valid READ operation the signals Strobe and R/W2 stay LOW while the signal R/W1 is always HIGH. For the valid WRITE operation the signal R/W2 always stays HIGH while the signals R/W1 and Strobe toggle. Table 3 represents the sequence of events as depicted in Figure 12 during the last channel at the end of an ST-BUS frame. The MT90210 device repeats the same sequence of operation during the entire frame. For example, during channel 127 at the end of an ST-BUS frame the MT90210 will write channel 126 (streams 0 to 11) and read from channel 1 (streams 12 to 23) of the next frame as shown in Table 3. Note that there is a two channel difference between a write and a read sequence. In mode 1 and mode 2, the MT90210 device performs a group of writes and a group of reads separated by 8 PCLK periods, while for modes 3, 4 and 5 they are separated by 4 PCLK periods.
1024 bytes for S16-S23 TX
BLOCK 0
512 bytes for S0-S15 RX
0800 09FF 0C00
1024 bytes for S16-S23 RX
512 bytes for S0-S15 TX
1000 11FF 1400
1024 bytes for S16-S23 TX
BLOCK 1
512 bytes for S0-S15 RX
1800 19FF 1C00
1024 bytes for S16-S23 RX
1FFF S0-S15 bidirectional 2.048Mb/s streams S16-S23 bidirectional 8.192Mb/s streams Address outputs used: A0-A12 Legend: unused memory space
Functional operation of the MT90210 device at the parallel interface for mode 4 and mode 5
Table 4 represents the sequence of events when the MT90210 device is operating at a mixed rate of operation (mode 4 and mode 5) as depicted in Figure 13. The MT90210 device repeats the same sequence of operation as shown in Table 4 throughout the entire frame. In mode 4 and mode 5 the MT90210 device is configured with 24 bidirectional serial streams and split into two different rates: S0 to S15 operate at 2.048 Mb/s data rates (512 time-slots) and streams S16 to S23 run at 8 Mb/s data rates (1024 time-slots). In this mode, 12 writes are carried out during a parallel port write cycle and 12 reads during a read cycle. Of each group of 12, 8 are dedicated to the high-speed 8.192 Mb/s links, therefore four slots are available for the 2.048 Mb/s links. To process all the 16 streams devoted for 2.048 Mb/s, four separate write or read cycles are required (these slots are denoted with the suffix "a", "b", "c", "d" in Figure 13). Each write or read cycle will use four time-slots. For example, read or write cycle "a" uses streams S0 to S3, read or write cycle "b" uses streams S4 to S7, read or write cycle "c" uses streams S8 to S11 and read or write cycle "d" uses streams S12 to S15 (see Table 4). There is a two channel difference between a read and write sequence for 2 Mb/s data and an eight channel difference for 8 Mb/s data.
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Figure 5- External Double Buffer Operation and Memory Arrangement in Modes 4 and 5. Bidirectional Operation: Serial output channel timeslots can be tri-stated by setting the OEser input pin high during a specific parallel channel timeslot. Note that when operating in bidirectional mode, the MT90210's I/O buffers on the serial port are permanently at high impedance and the control of contention on the serial bus has to be done by the user through the OEser input pin. In modes 1, 2, 4 and 5 all of the transmit channels on the serial port side are copied back to the memory interface. This is true only in bidirectional modes (i.e., modes 1, 2, 4 and 5). Note that only the transmit (output) channels are copied back to the memory and that the input channels remain unaffected. For a specific time-slot sampled at the external memory parallel interface, the respective OEser input pin must be in the desired state; i.e., the sampling of the OEser input is synchronized with the parallel byte read at the P0-P7 lines.
MT90210
Frame Boundary Established by F0i
Preliminary Information
SCLK (4 MHz) SCLK (8 MHz) SCLK, C16 (16 MHz) F0i
Serial I/O 2 Mb/s
Ch. 31, Bit 1
Ch. 31, Bit 0
Ch. 0, Bit 7
Ch. 0, Bit 6
Serial I/O 4 Mb/s
Ch. 63, Bit 2
Ch. 63, Bit 1
Ch. 63, Bit 0
Ch. 0, Bit 7
Ch. 0, Bit 6
Ch. 0, Bit 5
Serial I/O 8 Mb/s
Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 0, Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Ch. 0, Bit 6
Ch. 0, Bit 5
Ch. 0, Bit 4
Ch. 0, Bit 3
Ch. 0, Bit 2
Figure 6 - Serial Port Functional Timing
last write address of frame n
W R I T E
A0-A12
address x
inactive
P0-P7
Data Out
Data Out
inactive
WBC
MT90210 finishes writing data from frame n.
MT90210 will handle parallel port transactions related to frame n +1.
last read address of frame n
R E A D
A0-A12
address y
inactive
P0-P7
Data In
Data In
inactive
WBC
MT90210 finishes reading data from frame n.
MT90210 will handle parallel port transactions related to frame n +1.
Figure 7a - WBC and RBC Output Transition
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Preliminary Information
MT90210
RBC 125 us
WBC 125 us tNA Access of both Block 0 & Block 1 tNA Access of both Block 0 & Block 1
Exclusive access of Block 0
Exclusive access of Block 1
Exclusive access of Block 0
tNA ~ 1 timeslot for modes 1, 2 & 3 tNA ~ 3 timeslots for modes 4 & 5
Figure 7b - WBC and RBC operation in relation to accessing data from Block 0 and Block 1
SCLK
PCLK
A0-A12
ARD
ARD
AWR
AWR Toggles only during write data cycle Changes state (high to low) on every change of a block of reads or block of writes Low during read cycle, high during inactive periods and toggles during write cycles
R/W1
R/W2
Strobe
P0-P7
RD
RD
WR
WR
Note: The MT90210 device performs groups of writes and groups of reads separated by 4 inactive PCLK periods for modes 3, 4 and 5. In mode 1 and mode 2, the write and read groups are separated by 8 PCLK periods.
Figure 8 - Parallel Port Functional Read/Write Operation
JTAG Support
The MT90210 JTAG interface is designed according to the Boundary-Scan standard IEEE1149.1. The standard specifies a design-for-testability technique called Boundary-Scan Test (BST). A boundary-scan IC has a shift-register stage or `Boundary-Scan Cell' (BSC) in between the core logic and the I/O buffers adjacent to each I/O pin. The BSCs can control and observe what happens at each I/O pin of the IC. The operation of the boundary-scan circuitry is controlled by a Test Access Port (TAP) Controller.
Test Access Port (TAP) The Test Access Port (TAP) provides access to many test support functions built into the MT90210. It consists of three input connections and one output connection. The following connections form the TAP: * Test Clock Input (TCK) * Test Mode Select Input (TMS) * Test Data Input (TDI) * Test port Reset (TRST) * Test Data Output (TDO)
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MT90210
I[0:1] [00] Instruction EXTEST Description
Preliminary Information
Boundary-Scan This instruction is specifically provided to allow board-level interconnect register selected, testing of opens, bridging errors etc. Test Enabled When the EXTEST instruction is selected, the on-chip logic is isolated from the MT90210's I/O pin such that the value of the I/O pins is determined by its boundary-scan register. Data for the execution of this instruction can be preloaded into the boundary-scan register with the SAMPLE/PRELOAD instruction. Boundary-Scan Two functions can be performed by the use of this instruction. It allows a register selected, SAMPLE (`snapshot') of the normal operation of the MT90210 to be Test Disabled taken for examination. And, prior to the selection of another test operation, a PRELOAD can place data values into the latched parallel outputs of the Boundary-Scan cells. During the execution of the instruction, the on-chip logic operation is not hampered in any way. Bypass register selected, Test Disabled This instruction is used to BYPASS the MT90210 while performing boundary-scan testing on other devices with scan registers in the same serial register chain. The MT90210 is allowed to function normally. This instruction is automatically loaded upon reset of the MT90210, as specified in IEEE1149.1 Table1 - Instruction Register
[01], SAMPLE/ [10] PRELOAD
[11]
BYPASS/ NOTEST
Instruction Register In accordance with the IEEE 1149.1 standard, the MT90210 uses public instructions listed in Table 1. The MT90210 JTAG Interface contains a two bit instruction register. Instructions are serially loaded into the Instruction Register from the TDI when the TAP Controller is in its Shift-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. Test Data Registers As specified in the IEEE 1149.1 Standard, the MT90210 JTAG interface contains two test data registers: * The Boundary Scan Register * The Bypass Register The MT90210 boundary-scan register contains 144 bits. Bit 144 in Table 2 is the first bit clocked out. All tristate enable bits are asserted high: a logic 1 enables the corresponding group of outputs/bidirectionals. Note that clocking all zeros into the scan path register will set all outputs to tristate. Bits 1:60 61 62 63 64 65 66:68 69 70 71:72 73:76 77:100 101:102 103:128 129:130 131:132 133:144 Definition S4 - S23 RDIN OEser SCLK HC4 F0i MD2 - MD0 RST PCLK CKO R/W1 - R/W2 P0 - P7 Strobe A0 - A12 RBC WBC S0 - S3 BSC Type B I I I I I I I I O O B O O O O B
Table 2 - Boundary Scan Register
B - bidirectional: input cell, output cell followed by
tristate cell. I - input: input cell. O - output: output cell, followed by tristate cell.
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Preliminary Information
MT90210
ST-BUS SCSA MVIP H-MVIP
24
S0-S23
+5V
DUAL PORT RAM* +5V SEML SEMR CER OER
Strobe Mode 1: 4.096 MHz Mode 2: 8.192 MHz Mode 3 & 4: 16.384 MHz 8 kHz F0i Mode 5: 16.384 MHz Mode 5: 16.384 MHz C16Mode 4 & 5: 4.096 MHz HC4 C16+ P7-P0
13 9
CEL OEL 9th bit External
R/W2 SCLK OEser
I/O8L-I/O0L A12L-A0L I/O8R-I/O0R A12R-A0R
9
A12-A0
R/W1 +5V MT90210
R/WL
13
MS
R/WR
RDin BOUNDARY SCAN CONNECTOR
5
TRST TDI,TDO TMS,TCK
PCLK CKout
PLLAGND LP1 LP2
RST WBC RBC Interface to PC Bus and/or hardware control for monitoring purpose MD0 MD1 MD2 (Customer Specific Control Logic)
* Note: Dual Port RAM: Cypress part number: CY7B145-15 and IDT part number IDT7015
Figure 9 - Functional Example of the MT90210 Application Circuit
Applications
The MT90210 device may be used in applications such as video and teleconferencing bridge cards and voice processing cards for CTI (Computer Telephony Integration). MT90210 transfers all TDM channels of the ST-BUS interface into an external buffer. This eliminates long answer time and permits fast DSP access to ST-BUS, SCSA, MVIP or H-MVIP serial TDM buses. The MT90210 component can be set in H-MVIP mode with 24 fully bidirectional serial streams that are configured in different data rate combinations. Two data I/O subsets of H-MVIP are
provided by the MT90210: (i) the 24/2 mode in which all 24 lines operate at 2.048 Mb/s and (ii) the mixed rate of operation in which 16 streams operate at 2.048 Mb/s and the remaining 8 streams operate at 8.192 Mb/s data rates. When operating at 8.192 Mb/s rates, the MT90210 automatically terminates the C16+ and C16- differential clocks specified by the H-MVIP specifications. Figure 9 shows a functional block diagram of the MT90210 in a typical application.
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MT90210
Preliminary Information
PLLAGND
MT90210
C1 LP1 C2 R2 R1 LP2
R1= 3k R2= 100 + 5% C1= 10nF + 5% C2= 20pF
Figure 10 - Analog PLL Low Pass Filter Circuit
PLL Considerations
+5V
The MT90210 device contains an analog PhaseLocked Loop (PLL) which is used to create a higher speed clock for parallel port operation from the input SCLK. This analog PLL requires a loop filter circuit to be connected to the LP1 and LP2 pins, as shown in Figure 10. Additionally, the following design considerations are recommended for the PLL circuitry: * * Phase tolerance and jitter are independent of the PLL frequency. Jitter is affected by the noise on the PLLVDD and PLLVSS pins. It will increase if the noise level increases and is recommended to be kept less than 10 MHz on PLLVDD. Use of a C2 capacitor of 15-25pF (+10%) is recommended to reduce jitter. The components should be connected within one inch (1") of the package. Use a wide PCB trace for PLLVDD and PLLVSS separate from the device VDD/VSS connections. In some setups, an RC network (Figure 11) between PLLVDD and PLLVSS supplies helps to reduce jitter.
MT90210
100
PLLVDD
1.0nF
PLLVSS
Figure 11 - PLLVDD/PLLVSS RC Circuit
* * *
*
2-156
Preliminary Information
MT90210
Write wr wr wr wr wr wr wr wr wr wr wr wr Channel 126 126 126 126 126 126 126 126 126 126 126 126 INACTIVE Stream 0 1 2 3 4 5 6 7 8 9 10 11 Memory Address 0DE8h 0DE9h 0DEAh 0DEBh 0DECh 0DEDh 0DEEh 0DEFh 0DF0h 0DF1h 0DF2h 0DF3h
PCLK Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 to 16 17 18 19 20 21 22 23 24 25 26 27 28 29 to 32
Read -
rd rd rd rd rd rd rd rd rd rd rd rd
-
0 0 0 0 0 0 0 0 0 0 0 0
0 1 2 3 4 5 6 7 8 9 10 11
1000h 1001h 1002h 1003h 1004h 1005h 1006h 1007h 1008h 1009h 100Ah 100Bh
-
INACTIVE Table 3 - Functional Example of the Read and Write Operation (Mode 3)
2-157
MT90210
PCLK Cycle 1 Read Write wr 8Mb/s Channel 124 . . 8 9 10 11 12 13 . . 16 17 to 24 25 to 28 29 to 32 33 to 40 41 to 44 45 to 48 49 to 56 57 to 60 61 to 64 65 to 72 73 to 76 77 to 80 81 to 88 89 to 92 93 to 96 97 to 104 105 to 108 109 to 112 113 to 120 121 to 124 rd 7 wr wr 127 rd rd 6 wr wr 126 rd rd 5 wr wr 125 rd rd
-
Preliminary Information
8 Mb/s Stream 16
2 Mb/s Channel -
2 Mb/s Stream -
Memory Address 0FE0h
-
wr wr wr wr wr
124 -
23 -
31 31 31 31
0 1 2 3
0FE7h 09F0h 09F1h 09F2h 09F3h
INACTIVE
4 -
16 to 23 INACTIVE 16 to 23 INACTIVE 16 to 23 INACTIVE 16 -23 INACTIVE 16 to 23 INACTIVE 16 to 23 INACTIVE 16 to 23
1
0 to 3
0420h to 0427h 0010h to 0013h
31
4 to 7
0FE8h to 0FEFh 09F4h to 09F7h
1
4 to 7
0428h to 042Fh 0014h to 0017h
31
8 to 11
0FF0h to 0FF7h 09F8h to 09FBh
1
8 to 11
0430h to 0437h 0018h to 001Bh
31
12 to 15
0FF8h to 0FFFh 09FCh to 09FFh
-
-
0438h to 043Fh
rd 1 12 to 15 001Ch to 001Fh Table 4 - Functional Example of the Parallel Interface for Mode 4 and 5
2-158
Preliminary Information
MT90210
F0i S23:S0 Frame n, last channel Frame n+1, channel 0
P7:P0
Write data from S23-S0 frame n, 2nd last channel
Read data for S23-S0 frame n+1, channel 0
Write data from S23-S0 frame n, last channel
Read data for S23-S0 frame n+1, channel 1
Finished reading last channel of frame n RBC
WBC Finished writing last channel of frame n R/W1
R/W2 STROBE
Figure 12 - Modes 1, 2, 3 Read/Write Timing
2-159
MT90210
2M ts Frame n, channel 31
Preliminary Information
Frame n+1, channel 0
8M ts
ch 124
ch 125
ch 126
ch 127
ch 0
ch 1
ch 2
ch 3
3 channel delay for 8 Mb/s rate P7:P0 W8 121 W2 30b W8 123 W2 30d W8 125 W2 31b W8 127 W2 31d W8 120 W2 30a W8 122 W2 30c W8 124 W2 31a W8 126 W2 31c R8 127 R2 31d R8 1 R2 0b R8 3 R2 0d R8 5 R2 1b R8 7 R2 1d R8 0 R2 0a R8 2 R2 0c R8 4 R2 1a R8 6 R2 1c
Finished reading last channel of 8Mb/s and 4th quarter of last channel of 2 Mb/s of one complete frame(125 us) RBC
"a" denotes data for S0-S3 "b" denotes data for S4-S7 "c" denotes data for S8-S11 "d" denotes data for S12-S15
WBC
Finished writing last channel of 8 Mb/s and 4th quarter of last channel of 2 Mb/s
R/W1
R/W2
STROBE
Figure 13 - Mode 4 and Mode 5 Read/Write Timing
Mode 1 1 2 2 3 3 4 or 5 (@ 2M) 4 or 5 (@ 2M) 4 or 5 (@ 8 M) 4 or 5 (@ 8M)
TX/RX TX RX TX RX TX RX TX RX TX RX
Memory Address Location Formula for Block 0 24C + S 24C + S + 0400h 24C + S 24C + S + 0800h 12C + S 12C + S + 0800h 16C + S 16C + S + 0800h 8C + (S-16) + 0400h 8C + (S-16) + 0C00h
Memory Address Location Formula for Block 1 24C + S + 800h 24C + S + C00h 24C + S + 1000h 24C + S + 1800h 12C + S + 1000h 12C + S + 1800h 16C + S + 1000h 16C + S + 1800h 8C + (S-16) + 1400h 8C + (S-16) + 1C00h
Table 5 - Memory Address Location Formulae for all modes of operation
C = channel number, S = stream number
2-160
Preliminary Information
Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated.
Parameter 1 2 3 4 DC Power Supply Voltage VDD to VSS Voltage on any pin (other than supply pins) Current at any pin (except VDD and VSS) Package Power Dissipation Symbol VDD Vi IO PD VSS+0.3 Min
MT90210
Max 6 VDD+0.3 40 2
Units V V mA mW
*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated
Characteristics 1 2 Operating Temperature Power Supply Voltage Sym TOP VDD Min -40 4.75 Typ 25 5.0 Max +85 5.25 Units C V Test Conditions
DC Electrical Characteristics
Characteristics 1 2 3 4 5 6 Supply Current Input High Voltage, all inputs Input Low Voltage, all inputs Specific Output High Sourcing Current Specific Output Low Sinking Current Leakage Current S0-S23 All other pins Pin Capacitance Sym IDD VIH VIL IOH IOL ILK 200 5 CP 10 pF 2.0 0 12 12 Min Typ* 15 Max 100 VDD 0.8 Units mA V V mA mA A VOH=2.4V VOL=0.4V Test Conditions
7
DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25C and are for design aid only.
2-161
MT90210
Preliminary Information
AC Electrical Characteristics-The following table specifies voltage reference levels used in both input timing and output
timing specifications. The setup/hold and propagation delays are based on a single reference level which is 1.5V for TTL(VTT) and 0.5*VDD for CMOS (VCT).
Voltage Reference VH VHM VLM VL VTT VCT
Voltage Value when Connected to TTL 2.4 2.0 0.8 0.4 1.5 not applicable
Voltage Value when Connected to CMOS 0.9*VDD 0.7*VDD 0.3*VDD 0.1*VDD not applicable 0.5*VDD
Units V V V V V V
VH VTT
VH VTT
t
VL
t
VL
Figure 14 - Input Pulse Width
VH VHM VLM VL
t
t
Figure 15 - Input Rise and Fall Times
VH Clock VTT VL
t
Input Data
t
VH VTT VL
Figure 16 - Setup Time and Hold Time
2-162
Preliminary Information
MT90210
VH
clock
VTT VL
t
drive to drive output
VTT
t
drive to hiz-low output
t
drive to hiz-high output
Figure 17 - Output Delays
tfrw
F0i
tfrs tclk
tfrh
tclkl
SCLK 4.096 MHz (Mode 1) 8.192 MHz (Mode 2) 16.384 MHz (Mode 3)
tT
tclkh
tstis
S0-23
tstih
bit 0, last ch tstod bit 0, last ch bit 7, ch.0
bit 7, ch.0
(inputs)
S0-23
(outputs)
Mode
1, last channel = 31 Mode 2, last channel = 63 Mode 3, last channel = 127
Figure 18 - Serial Port Timing for Modes 1, 2, 3
2-163
MT90210
thfrw F0i (8kHz) tfrs tfrh tstis S0-15 (2.048 Mb/s) (inputs) S0-15 (2.048 Mb/s) (outputs) bit 0, ch. 31 tstih
Preliminary Information
bit 7, ch. 0
tstod
bit 0, ch. 31 bit 7, ch. 0
thclk
tT thclkh
HC4 (4.096 MHz)
thclkl tclkl
tch
(16.384 MHz)
tstih tclkh tclk tstis
bit 7, ch.127 bit 0, ch0 bit 1, ch.0
S16-S23 (8.192 Mb/s) (inputs) S16-S23 (8.192 Mb/s) (outputs)
tstod
bit 1, ch. 127 bit 0, ch. 127 bit 7, ch. 0 bit 1, ch. 0
Figure 19 - Serial Port Timing for Modes 4 and 5
bit cell boundary
SCLK, C16+
tza
S0-23
taz
S0-23
Figure 20 - Serial Port Tri-state Timing
2-164
Preliminary Information
AC Electrical Characteristics
Characteristics 1 SCLK, C16 Period 2.048 Mb/s (4.096 MHz) 4.096 Mb/s (8.192 MHz) 8.192 Mb/s (16.384 MHz) SCLK, C16 Pulse Width High 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s SCLK, C16 Pulse Width Low 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s SCLK rise/fall time HC4 hold related to C16 HC4 period HC4 pulse low HC4 pulse high Frame Pulse Setup (ST-BUS) Sym tclk 244 122 60 tclkh 122 60 30 tclkl 122 60 30 tT tch thclk thclkl thclkh tfrs tfrh tfrw 244 122 60 thfrw taz 30 tza 30 tstod 30 tstis tstih 0 ns 10 ns ns ns ns ns 244 ns ns ns ns 0 10 3 244 122 122 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Typ* Max Units
MT90210
Test Conditions
2
3
4 5 6 7 8 9
10 Frame Pulse Hold (ST-BUS) 11 Frame pulse width in modes 1,2,3 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s 12 Frame pulse width in modes 4,5 13 S0-23 delay from active to High-Z 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s 14 S0-23 delay from High-Z to active 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s 15 S0-23 Delay (high and low) from CLK falling (ST-BUS mode) 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s 16 S0-23 Set-up Time before CLK rising (ST-BUS mode) 17 S0-23 Hold Time from CLK rising (ST-BUS mode)
RL=1K, CL=200pF
RL=1K, CL=200pF
RL=1K, CL=200pF
18 CKout output delay from SCLK tdpll 5 DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25C and are for design aid only.
2-165
MT90210
Preliminary Information
CKout (mode 3/4/5)
tdpll
SCLK
C16+
C16 -
Figure 21 - PLL Timing
SCLK or C16+, C16CKout (16.384 MHz, mode 1) (32.768 MHz, mode 2/3/4/5)
tad
A0-A12
X
Y
Z
RDin input
tst
P0-P7 (Read/ Write)
thd
X(rd) Y(rd) Z(rd)
tstb
Strobe
toes
OEser input
toeh Valid
Valid
Note: R/W1 output signal is HIGH and R/W2 output signal is LOW during read cycles.
Figure 22 - Parallel Port Data Read Cycle
2-166
Preliminary Information
MT90210
SCLK or C16+, C16 CKout (16.384 MHz, mode 1) (32.768 MHz, mode 2/3/4/5)
tad
A0-A12
X
Y
Z
S
tr/wd
R/W1
tah
tdod
P0-P7 (Read/ Write) WR(x) WR(y) WR(z)
tpwe
tstb
Strobe
tpwe
Note: R/W2 output signal is HIGH during write cycles.
Figure 23- Parallel Port Data Write Cycle
AC Electrical Characteristics
Characteristics 1 2 3 Address Output Delay from Clock Output Delay on R/W1 and Strobe Pulse Width Low - R/W1 and Strobe modes 2, 3, 4 & 5 mode 1 Internal Data Output Delay from Clock Falling Address Hold from Write Inactive Input Data & OE setup times Input Data & OE hold times Sym tad tr/wd, tstb tpwe 13.5 30 tdod tah tst, toes thd, toeh 2.25 0 5 10 ns ns ns ns Min Typ* Max 15 9.5 Units ns ns ns pulse width low on PCLK for 30 ns output load 50 pF Test Conditions output load 50pF
4 5 6 7
DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25C and are for design aid only.
2-167
MT90210
Preliminary Information
2-168
Package Outlines
L1 A A2 L b
A1
e
D D1
E1
Index
E
Notes: 1) Not to scale 2) Top dimensions in inches 3) The governing controlling dimensions are in millimeters for design purposes ( )
WARNING: This package diagram does not apply to the MT90810AK 100 Pin Package. Please refer to the data sheet for exact dimensions. Pin 1
Metric Quad Flat Pack - L Suffix
44-Pin
Dim
64-Pin Max
0.096 (2.45) 0.083 (2.10) 0.018 (0.45)
100-Pin Max
0.134 (3.40) 0.12 (3.05) 0.02 (0.50)
128-Pin Max
0.134 (3.40) 0.12 (3.05) 0.015 (0.38)
Min
A A1 A2 b D D1 E E1 e L L1 0.01 (0.25) 0.077 (1.95) 0.01 (0.30)
Min
0.01 (0.25) 0.1 (2.55) 0.013 (0.35)
Min
0.01 (0.25) 0.1 (2.55) 0.009 (0.22)
Min
0.00 0.125 (3.17) 0.019 (0.30)
Max
0.154 (3.85) 0.01 (0.25) 0.144 (3.60) 0.018 (0.45)
0.547 BSC (13.90 BSC) 0.394 BSC (10.00 BSC) 0.547 BSC (13.90 BSC) 0.394 BSC (10.00 BSC) 0.031 BSC (0.80 BSC) 0.029 (0.73) 0.04 (1.03)
0.941 BSC (23.90 BSC) 0.787 BSC (20.00 BSC) 0.705 BSC (17.90 BSC) 0.551 BSC (14.00 BSC) 0.039 BSC (1.0 BSC) 0.029 (0.73) 0.04 (1.03)
0.941 BSC (23.90 BSC) 0.787 BSC (20.00 BSC) 0.705 BSC (17.90 BSC) 0.551 BSC (14.00 BSC) 0.256 BSC (0.65 BSC) 0.029 (0.73) 0.04 (1.03)
1.23 BSC (31.2 BSC) 1.102 BSC (28.00 BSC) 1.23 BSC (31.2 BSC) 1.102 BSC (28.00 BSC) 0.031 BSC (0.80 BSC) 0.029 (0.73) 0.04 (1.03)
0.077 REF (1.95 REF)
0.077 REF (1.95 REF)
0.077 REF (1.95 REF)
0.063 REF (1.60 REF)
NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters.
Package Outlines
160-Pin
Dim
208-Pin Max
0.154 (3.92) 0.01 (0.25) 0.01 (0.25) .126 (3.20) .007 (0.17) 1.204 (30.6) 1.102 (28.00) 1.204 BSC (30.6 BSC) 1.102 BSC (28.00 BSC) 0.020 BSC (0.50 BSC) 0.04 (1.03) 0.018 (0.45) 0.051 REF (1.30 REF) 0.029 (0.75) 0.018 (0.45)
240-Pin Max
.161 (4.10) 0.02 (0.50) .142 (3.60) .011 (0.27)
Min
A A1 A2 b D D1 E E1 e L L1 0.029 (0.73) 0.063 REF (1.60 REF) 0.125 (3.17) 0.009 (0.22) 1.23 BSC (31.2 BSC) 1.102 BSC (28.00 BSC) 1.23 BSC (31.2 BSC) 1.102 BSC (28.00 BSC) 0.025 BSC (0.65 BSC) -
Min
Min
0.01 (0.25) 0.126 (3.2) 0.007 (0.17) 1.360 BSC (34.6 BSC) 1.26 BSC (32.00 BSC) 1.360 BSC (34.6 BSC) 1.26 BSC (32.00 BSC) 0.0197 BSC (0.50 BSC)
Max
0.161 (4.10) 0.02 (0.50) 0.142 (3.60) 0.010 (0.27)
0.144 (3.67) 0.015 (0.38)
0.029 (0.75) 0.051 REF (1.30 REF)
NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters.
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